1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a function of data compressing test hat efficiently executes a read/write operation test by compressing data signals.
2. Description of the Related Art
The memory capacity of memory LSI such as DRAM (Dynamic Random Access Memory) has been increasing every year. Because of the increase of the memory capacity, the address spaces of these memory LSI can be sufficiently secured even in the case where the input/output terminals are 16 bits or 32 bits (in general, referred to as plural bits products). For example, a work memory that is used for a 32-bit microcomputer can be constructed using a single 32-bit memory LSI.
On the other hand, as the number of external terminals increases, the number of memory LSI that can be mounted on a test-use evaluation board tends to decrease. The efficiency of testing the memory LSI depends on the number of the input/output terminals of an LSI tester. For example, if the number of the input/output channels of an LSI tester is 256, 32 of DRAMs each having 8-bit input/output terminals can simultaneously are tested; however, only eight of DRAMs each having 32-bit input/output terminals can simultaneously be tested. As a result, the testing cost (especially testing for shipment) significantly increases.
Recently, to prevent the increase of the testing cost due to the increase of the input/output terminals, a memory LSI that has a data compression function of efficiently executing the read/write operation test by compressing data signals within the memory LSI has been developed.
FIG. 1 shows a memory core 10 of an SDRAM (Synchronous DRAM) having the data compressing function. This SDRAM has 32-bit input/output terminals. Each bit of the input/output data transmitted through input/output terminals also is referred to as DQ hereafter.
The memory core 10 has ninety-six memory cell arrays 12 (memory cell regions) that are arranged in eight rows in the vertical direction and in twelve columns in the horizontal direction in the figure.
One row of the memory cell arrays 12 is assigned one of blocks BLK0 to BLK7. The blocks BLK0, BLK4, blocks BLK1, BLK5, blocks BLK2, BLK6, and blocks BLK3, BLK7, respectively, are activated at the same time. The twelve memory cell arrays 12 that are constructed of four rows xc3x97 three columns (reference characters A to H in the figure) correspond to predetermined DQs. The memory cells assigned character A correspond to DQ0, DQ1, DQ14, and DQ15. The memory cells assigned character B correspond to DQ2, DQ3, DQ12, and DQ13. The memory cells assigned character C correspond to DQ4, DQ5, DQ10, and DQ11. The memory cells assigned character D correspond to DQ6, DQ7, DQ8, and DQ9. The memory cells assigned character E correspond to DQ18, DQ19, DQ28, and DQ29. The memory cells assigned character F correspond to DQ16, DQ17, DQ30, and DQ31. The memory cells assigned character G correspond to DQ22, DQ23, DQ24, and DQ25. The memory cells assigned character H correspond to DQ20, DQ21, DQ26, and DQ27. Regions of memory cell arrays assigned characters A to H, each of which is constructed of twelve memory cell arrays 12, will be also referred to as groups A to H, respectively, hereafter.
Outside each of the groups B, D, F, and H, a column decoder 14 is arranged. A row decoder 16 is arranged between groups C, D and groups E, F. Word lines WL are wired to extend from the row decoder 16 towards the memory cell arrays 12 at both sides in the horizontal direction.
Between the memory cell arrays 12, a plurality of main data line pairs MDLP is wired along the vertical direction of the figure, and a plurality of sub data line pairs SDLP is wired along the horizontal direction. The sub data line pairs SDLP are connected to the main data line pairs MDLP by data line switches 18 indicated by black dots. That is, the data lines have a hierarchical structure. The groups A, B, the groups C, D, the groups E, F, and the groups G, H have the same structure (including mirror symmetry), respectively, except for the DQ numbers. Because of this, groups A, B are mainly explained hereinafter.
FIG. 2 shows the detailed layout of the groups A, B.
For each memory cell array 12, a plurality of bit line pairs BLP is wired along the vertical direction of the figure. In order to avoid interference, each bit line pair BLP is wired between bit line pairs BLP of other bit numbers. The bit line pairs BLP are connected to the sub data line pairs SDLP by column line switches 20, which are indicated by outline dots. The bit line pairs BLP, which are connected to a column line switch 20 formed between particular blocks (between BLK1 and BLK2, for example), are wired into the respective blocks (BLK1 and BLK2). The bit line pairs BLP that are connected to the column line switch 20 formed outside the blocks BLK0, BLK3 are wired into the blocks BLK0, BLK3, respectively.
The arrows indicated by thick lines in the figure show the data flows of the read operation and write operation. For example, the data to be read from a memory cell array 12 in the block BLK1 of the group B is transmitted to the exterior of group B through bit line pair BLP, column line switch 20, sub data line pair SDLP, data line switch 18, and main data line pair MDLP (FIG. 2 (i)). The data to be written to memory cell array 12 in the block BLK 4 (group A) is transmitted from the exterior to a memory cell (not shown in the figure) through main data line pair MDLP, data line switch 18, sub data line pairs SDLP, column line switch 20, and bit line pair BLP (FIG. 2 (ii)).
Each block (for example, BLK0 constructed of groups B, D, F, H shown in FIG. 1) has two word line relief circuits 22. The word line relief circuit 22 has a redundancy word line (not shown in the figure) and a plurality of redundancy memory cells (not shown in the figure) connected to the redundancy word line. Using the word line relief circuits 22, the blocks BLK0 to BLK7 each can relieve two word line defects or two bit defects.
Each of groups A to H has at least one bit line relief circuit 24. The bit line relief circuit 24 has a redundancy bit line pair (not shown in the figure), and a plurality of redundancy memory cells (not shown in the figure) connected to the redundancy bit line pair. Using the bit line relief circuit 24, the groups A to H each can relieve one bit line defect or one bit defect.
FIG. 3 shows a control circuit 26 formed between the blocks BLK0 and BLK1.
Bit line pairs BLP of the blocks BLK0, BLK1 are connected to a shared bit line pair SHBLP through bit line switches 28, which consist of an nMOS transistor. The bit line switches 28 are controlled by control signals BT0, BT1, respectively, which are activated in accordance with the column address. A sense amplifier 30 and a precharge circuit 32 are connected to the shared bit line pair SHBLP. When equalizing signal BRS is at the high level, the precharge circuit 32 supplies precharge voltage VPR to the shared bit line pair SHBLP and to the bit line pairs BLP that are connected to the shared bit line pair SHBLP by the control signals BT0, BT1. The sense amplifier 30 and precharge circuit 32 are shared by the blocks BLK0 and BLK1 through the bit line switches 28. The shared bit line pair SHBLP is connected to the sub data line pair SDLP through column switch 20 consisting of nMOS transistors. The gate of the column switch 20 is controlled by a column line selecting signal CL, which is activated in accordance with the column address. A data line switch 18, which connects the sub data line pair SDLP to the main data line pair MDLP, is constructed of nMOS transistors and an inverter. The gates of the data line switch 18 are controlled by a precharge signal BRS through the inverter. For example, the read operation of the block BLK0 is executed by changing the control signal BT0 and the column line selecting signal CL to the high level, and changing the control signal BT1 and the precharge signal BRS to the low level, thereby connecting the bit line pair BLP of the block BLK0, the shared bit line pair SHBLP, the sub data line pair SDLP, and the main data line pair MDLP.
FIG. 4 shows the control circuit 34 that is formed between the blocks BLK3 and BLK4 (between the groups A and B).
Because groups A, B have different bit numbers (DQs) for the data retained, each group has a control circuit of its own. The gates of the bit line switches 28 that are connected to one end of the shared bit line pair SHBLP are connected to the ground line VSS, and the other ends of these bit line switches 28 at the opposite side with respect to the bit line pair BLP are left open. At the block BLK3, the precharge circuit 32 and the data line switch 18 receive precharge signal BRS3, the column line switch 20 receives column line selecting signal CL, and switches 28 that are connected to the bit line pair BLP receive control signal BT3. At the block BLK4, the precharge circuit 32 and the data line switch 18 receive precharge signal BRS4, the column line switch 20 receives column line selecting signal CL, and the bit line switches 28 that are connected to the bit line pair BLP receive the control signal BT4.
Thus, at the boundary part of the groups A and B, sense amplifiers 30, precharge circuits 32, and the like are arranged for each group. Due to this, the layout area between the blocks BLK3 and BLK4 needs to be larger than the areas between other blocks.
FIG. 5 shows the data compressing circuit 36 for the write data in the conventional SDRAM.
The data compressing circuit 36 has eight buffer circuits 38 corresponding to input/output data signals DQ0 to DQ7, respectively, and a selecting circuit 40. The buffer circuits 38 receive the input/output data signal DQ0 to DQ7, and output them as write data signals DINCZ0 to DINCZ7, respectively. The selecting circuit 40 receives write data signals DINCZ0 to DINCZ7, and enable signal TEST8 for compressing test, and outputs write data signals DIN0 to DIN7.
FIG. 6 shows the details of the selecting circuit 40.
The selecting circuit 40 is constructed of eight switching circuits 42 corresponding to write data signals DINCZ0 to DINCZ7, respectively, and inverters 40a, 40b, and 40c, which control the switching circuits 42. The switching circuits 42 each have a CMOS transmission gate 42a, which transmits a signal that is supplied to terminal D1 through an inverter, and a CMOS transmission gate 42b, which transmits a signal supplied to the terminal D2. The outputs of the CMOS transmission gates 42a and 42b are connected to each other, and are connected to the terminals D0 through two cascade-connected inverters. The CMOS transmission gates 42a and 42b are controlled by a signal that has the same phase as that of the enable signal TEST8 and also by a signal that has a phase opposite to that of the enable signal TEST8.
The CMOS transmission gate 42a is turned on when the enable signal TEST8 is at the low level (normal operation). The CMOS transmission gate 42b is turned on when the enable signal TEST8 is at the high level (data compressing test). The terminal D2 of each of the selecting circuits 42 receives the inverted signal of the write data signal DINCZ7 through the inverter 40c. That is, in the normal operation, the write data signals DINCZ 0-7 are transmitted as the write data signals DIN 0-7. When in the data compressing test, the 8-bit input/output terminals are compressed into 1-bit, and the write data signal DINCZ7 is transmitted as write data signals DIN 0-7. Although not particularly shown in the figure, the same structured selecting circuits 40 are formed for the input/output data signals DQ8 to DQ15, DQ16 to DQ 23, and DQ24 to DQ31, respectively.
An evaluation board of an LSI tester that evaluates this SDRAM can executes the read/write operation test for one SDRAM using only 4-bit (DQ7, DQ15, DQ23, DQ31) input/output channels. For example, it is feasible of testing as many as sixty-four SDRAMs at a time in an LSI tester having 256 input/output channels.
The data compressing tests are often executed for confirming operations of chips at the time of probe testing (the relief determination) when chips are still on wafers and at the time of final testing after package assembly.
Here, because such data compressing test compresses the input/output data when testing, in cases where a defect is found during the test, it cannot determine which bit of the input/output data has the defect. For example, as marked by xe2x80x9cxc3x97xe2x80x9d in FIG. 2, if the DQ2 of the block BLK0 actually has a bit defect, and a word line defect occurred, the data compressing test cannot determine which one of the groups A, B, C, and D has that defect. Because of this, in order to relieve this defect using word line relief circuits 22, the word line relief circuits 22 of both blocks BLK0, BLK4 have to be used. Thus, the relief efficiency (the usage efficiency of the word line relief circuits 22) is low because the word line in block BLK4 that is operating normally also is relieved. As a result, there were the problems of decrease in the yield and increase in the manufacturing cost.
The relief address, relief DQ, can be confirmed by the normal read/write operation test without using the data compressing test technique. However, in that case, the number of the memory LSIs that can be tested simultaneously by an LSI tester decreases (from sixty-four to eight memory LSI in the above-mentioned example). Accordingly, the manufacturing cost (testing cost) significantly increases.
It is possible to prevent the decrease in relief efficiency by adding data compressing test control circuits corresponding to the number of DQs (in the above example, 4-bit) of each memory cell array 12 and making variable the number of bits to be compressed. However, in this case, new selecting circuits other than the ones shown in FIG. 6 need to be formed. As a result, a larger layout size is necessary, resulting in an increase in chip size.
In addition, there has been a drawback that a layout size increases between the blocks BLK3 and BLK4 shown in FIG. 4 unlike between the other blocks because the sense amplifier 30 and the precharge circuit 32 are arranged for each of the blocks BLK3 and BLK 4.
An object of the present invention is to improve defect relief efficiency by using a data compressing test function.
Another object of the present invention is to reduce a semiconductor integrated circuit in chip size. Another object of the present invention is to reduce particularly a semiconductor integrated circuit having a data compressing test function in size.
According to one of the aspects of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit has a plurality of input/output terminals for transmitting input/output data, a plurality of memory cells for retaining the input/output data, a first switching circuit, and a plurality of second switching circuits. The first switching circuit selects data of a predetermined bit from the input/output data in accordance with each of a plurality of testing modes and outputs the selected data as testing data. The plurality of second switching circuits is formed in correspondence with the plurality of input/output terminals, respectively. The second switching circuits receive the testing data and each bit of the input/output data, and select one of the input/output data and the testing data in accordance with the operation mode. In detail, each bit of the input/output data is respectively outputted to the memory cells during normal operation mode. During testing mode the testing data is selected to be outputted to the memory cells as the common input/output data. That is, the data compressing test is executed. Thus, write control for multiple kinds of data compressing test can be performed by using the simple first and second switching circuits. As a result, the control circuit for the data compressing test can be reduced in layout size, whereby prevents increase in chip size. The load of data outputted from the second switching circuits does not fluctuate in the normal operation mode and in the plurality of testing modes because the testing data corresponding to the plurality of data compressing tests is selected by the first switching circuit. This facilitates timing design.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit has a plurality of memory cell arrays assigned a plurality of bits with different numbers from each other. Each memory cell array has a relief circuit for relieving a defect which occurs at a predetermined address. The number of the second switching circuits that receive single testing data in the testing mode is set less than or equal to the number of bits assigned to each memory cell array. In other words, the number of bits written testing data is less than or equal to the number of bits that is relieved at once by the relief circuit. This makes it possible to determine defects during the testing mode (data compressing test) for every memory cell array, which allows relief of the defects by using only the relief circuit in the memory cell array where a defect actually occurs. Even when the data compressing test is applied to relief determination, the efficient use of the relief circuit enables prevention of a decease in relief efficiency.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit has a latch, between the first switching circuit and the second switching circuits, for retaining testing data. Therefore, even when the output of the first switching circuit is at high impedance, a high or low level is supplied to the second switching circuits. This prevents malfunction of the second switching circuits and occurrence of a feedthrough current.
According to another aspect of the semiconductor integrated circuit in the present invention, the latch has a reset circuit for receiving a reset signal that is activated when the power is turned on and resetting the latch to a predetermined internal state. Thus, the latch is initialized with reliability when the power is on, thereby preventing occurrence of a feedthrough current.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit further has a buffer for providing input/output data to the second switching circuits. The first switching circuit is provided with input/output data transmitted at a node located between the input/output terminals and the buffer. Therefore, the loads of the input/output data supplied to the second switching circuits can be all equalized. This prevents an undesirable shift of timing of supplying a specific bit, that is to be used in the testing mode, to the second switching circuit.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit has a plurality of input/output terminals for transmitting input/output data, a plurality of memory cell regions, bit line switches corresponding to each memory cell region, and a sense amplifier. Each memory cell region is assigned bits with different numbers from each other, of the input/output data, and different addresses from each other. The bit line switches connect bit lines respectively connected to memory cells in each memory cell region, with shared bit lines. The sense amplifier connected to the shared bit lines, amplifies data on the bit lines that are transmitted through the bit line switches. For example, when a memory cell region is accessed, only the bit line switches corresponding to that memory cell array are turned on, and data of a specified bit among the input/output data is transmitted between the bit lines and the shared bit lines. The sense amplifier amplifies the data transmitted to the shared bit lines. When the other memory cell region is accessed, only the bit line switches corresponding to that memory cell region are turned on, and data of a different bit from the previous data among the input/output data is transmitted between the bit lines and the shared bit lines. The sense amplifier amplifies the different data transmitted to the shared bit lines. The sense amplifier is shared among the input/output data of different bits from each other. As a result, the sense amplifiers can be reduced in number, the memory cell regions can be reduced in layout size, and the chip size can be reduced.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit has data line switches for respectively connecting the shared bit lines and data lines corresponding to a predetermined bit assigned to each memory cell region. Therefore, data of a predetermined bit corresponding to the memory cell region is transmitted with certainty between the memory cell region and the data lines.
According to another aspect of the semiconductor integrated circuit in the present invention, the shared bit lines are respectively connected to two memory cell regions via bit line switches. A control signal for activating the bit line switches corresponding to the bit of one of memory cell region is used for inactivating the data line switch corresponding to the bit of the other memory cell region. That is, the bit lines in one memory cell region are activated while the bit lines in the other memory cell region are inactivated. Accordingly, the data line switches corresponding to the two memory cell regions are easily controlled without being formed a special signal generation circuit.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit has a testing mode in which the plurality of bit line switches are concurrently turned on to write input/output data at once to each of the memory cell regions. At least one data line switch is turned on during the testing mode so that input/output data can be written to memory cell regions corresponding to the other data lines by using a part of the data lines. That is, the data compressing test can be executed under simple control.
According to another aspect of the semiconductor integrated circuit in the present invention, turning on a plurality of bit line switches simultaneously makes it possible to activate all word lines connected to the memory cells to perform a burn-in test where the memory cells are applied stress.